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| Ordering number : EN*5154B CMOS LSI LC895194 CD-ROM Error Correction LSI with On-Chip ATA-PI (IDE) Interface Preliminary Functions CD-ROM error detection and correction, ATA-PI (IDE) interface (including the register and other blocks) Package Dimensions unit: mm 3214-SQFP144 [LC895194] Features * ATA-PI (IDE) interface * Supports 16x-speed playback (with IORDY): Using 16x 70 ns DRAMs * 16.6 MB/s transfer rate: Using 16x 70 ns DRAMs * Supports the use of from 1 M to 32 M of buffer RAM. (DRAM) * Allows the user to arbitrarily set the CD main channel and C2 flag areas in buffer RAM. * Batch transfer function (function for transferring the CD main channel and C2 flag data in one operation) * Multi-transfer function (function for sending multiple blocks in one operation) SANYO: SQFP144 Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering heat resistances (pins only) I/O power Note: * Per cell for basic I/O cells II, IO Symbol VDD max VI, VO Pd max Topr Tstg 10 seconds Ta = 25C Ta = 25C Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 550 -30 to +75 -55 to +125 235 20* Unit V V mW C C C mA Allowable Operating Ranges at Ta = -30 to +75C, VSS = 0 V Parameter Supply voltage Input voltage range Symbol VDD VIN Conditions min 4.5 0 typ 5.0 max 5.5 VDD Unit V V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3097HA(OT) /81095HA (OT) No. 5154-1/7 LC895194 DC Characteristics at VSS = 0 V, VDD = 4.5 to 5.5 V, Ta = -30 to +75C Parameter Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Input high level voltage Input low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output high level voltage Output low level voltage Output low level voltage Output low level voltage Input leakage current Output leakage current Pull-up resistance Pull-down resistance Input voltage hysteresis Symbol VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL VOH VOL VOH VOL VOH VOL VOL VOL IIL IOZ RUP RDN VHYS Applicable Pins* (See below) TTL compatible: (1) min 2.2 -- 2.2 -- 2.2 -- 2.4 -- 0.8 VDD -- VDD - 2.1 -- VDD - 2.1 -- VDD - 2.1 -- VDD - 2.1 -- -- -- -10 -10 40 40 0.8 typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 80 1.0 max -- 0.8 -- 0.8 -- 0.8 -- 0.8 -- 0.2 VDD -- 0.4 -- 0.4 -- 0.4 -- 0.4 0.4 0.4 +10 +10 160 160 1.3 Unit V V V V V V V V V V V V V V V V V V V V A A k k mV TTL compatible, with pull-up resistor: (13) TTL compatible, with pull-down resistor: (2) TTL compatible, Schmitt: (3), (5), and (14) COMS compatible, Schmitt: (4) IOH = -2 mA IOL = 2 mA IOH = -8 mA IOL = 8 mA IOH = 4 mA IOL = 24 mA IOH = -2 mA IOL = 2 mA IOL = 2 mA IOL = 24 mA (8), (10), and (13) (7) (9), and (14) (6) (11) (12) VI = VSS, VDD: (1), (3), (4), (9), and (14) For high-impedance outputs: (6), (12), and (14) (13) (2), (5) (3), and (14) Note: * The entries in the "Applicable Pins" column specify the following pin sets. [Input] 1: CSCTRL, SUA0 to SUA6 2: TEST0 to TEST4 3: DA0 to DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST, ZRESET, BCK, C2PO, LRCK, SDATA 4: ZCS, ZRD, ZWR 5: WFCK, SCOR [Output] 6: ZINT1 7: MCK, MCK2 8: ZINT, ZSWAIT 9: DMARQ, HINTRQ 10: RA0 to RA9, ZCAS0, ZCAS1, ZLWE, ZOE, ZRAS0, ZRAS1, ZUWE 11: ZRSTCPU, ZRSTIC 12: IORDY, ZIOCS16 [I/O] 13: D0 to D7, IO0 to IO15 14: DD0 to DD15, ZDASP, ZPDIAG Note: XTAL, XTALCK The above pins are not included in the DC characteristics. Sample Recommended Oscillator Circuit R1 = 120 k R2 = 47 k C1 = 30 pF For a crystal oscillator frequency of 16.9344 MHz. Alternatively: R1 = 3.3 k R2 = None C1 = 5 pF For a crystal oscillator frequency of 33.8688 MHz. For an oscillator frequency of 33.8688, the third harmonic is used. This means that precise component values will be influenced by the printed circuit board. Consult the manufacturer of the crystal to determine the circuit constants for this frequency. No. 5154-2/7 LC895194 Block Diagram Each block register R0 to R99 Note: 1. 2. 3. 4. 5. 6. 7. 8. 9. WFCK, SCOR BCK, SDATA, LRCK, C2PO DD0 to DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA0 to DA2, ZDIOR, ZDIOW, ZDMACK DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 to SUA6, ZCS, CSCTRL D0 to D7 IO0 to IO15 RA0 to RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE Note: HISIDE (WD25C32) is made by WESTERN DIGITAL. No. 5154-3/7 LC895194 Pin Functions Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 IO0 IO1 IO2 IO3 IO4 IO5 VSS0 VDD IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15 EXCK WFCK SBSO SCOR TEST0 TEST1 TEST2 TEST3 Symbol VSS0 ZRAS0 ZRAS1 VSS0 ZCAS0 ZCAS1 VSS0 ZOE ZUWE ZLWE RA0 RA1 RA2 RA3 RA4 RA5 RA6 VDD VSS0 RA7 RA8 RA9 Type P O O P O O P O O O O O O O O O O P P O O O NC NC NC NC NC NC NC B B B B B B P P B B B B B B B B B B O I I I SUB-CODE input/out pin Data buffer RAM data I/O These pins have built-in pull-up resistors. Data buffer RAM data I/O These pins have built-in pull-up resistors. Test pins. RA0 to RA9 are the data buffer DRAM address lines. RA0 to RA9 are the data buffer DRAM address lines. Buffer RAM output enable Buffer RAM upper write enable Buffer RAM lower write enable Buffer DRAM CAS signal output 0 (This pin is used normally.) Buffer DRAM CAS signal output 1 Buffer DRAM RAS signal output 0 (This pin is used normally.) Buffer DRAM RAS signal output 1 Function Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Continued on next page. No. 5154-4/7 LC895194 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VSS0 SDATA BCK LRCK C2PO MCK2 VSS0 XTALCK XTAL VSS0 VDD MCK VSS0 ZRSTIC CSCTRL ZRESET ZRD ZWR ZCS VSS0 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VDD VSS0 D0 D1 D2 D3 D4 D5 D6 D7 ZINT Symbol VSS0 VSS0 TEST4 VSS0 VSS0 ZINT1 VSS0 VSS0 VSS0 Type P P I P P O P P P NC NC P I I I I O P I O P P O P O I I I I I P I I I I I I I P P B B B B B B B B O Interrupt request signal output to the microcontroller Microcontroller data signals These pins have built-in pull-up resistors. Microcontroller register select signals Reset signal to drive reset IC Selects active high or active low for the microcontroller CS line. LSI reset Microcontroller data read signal input Microcontroller data write signal input Input for the register chip select signal from the microcontroller XTALCK 1/1, 1/2, and stop output Crystal oscillator input Crystal oscillator output XTALCK 1/1, 1/2, 1/512, and stop output CD-DSP interface Interrupt request signal output to the microcontroller from the IDE block Test input. This pin must be tied low. Function Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Continued on next page. No. 5154-5/7 LC895194 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Symbol ZRSTCPU ZSWAIT ZHRST ZDASP ZCS3FX ZCS1FX DA2 VSS0 VDD DA0 ZPDIAG DA1 ZIOCS16 HINTRQ ZDMACK VSS1 IORDY ZDIOR ZDIOW DMARQ DD15 VSS1 DD0 DD14 DD1 DD13 VSS1 VDD DD2 DD12 DD3 VSS1 DD11 DD4 DD10 VSS1 VDD DD5 DD9 DD6 VSS1 DD8 DD7 VDD Type O O I B I I I P P I B I O O I P O I I O B P B B B B P P B B B P B B B P P B B B P B B P ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI control signals ATAPI control signals ATAPI control signals Reset signal to CPU Wait signal output to the microcontroller Function Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. No. 5154-6/7 LC895194 s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5154-7/7 |
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